IC chip using a phase-locked loop for providing signals having different timing edges

ABSTRACT

An integrated circuit chip having improved on-chip circuitry including a phase-locked-loop for providing accurately timed signal having different durations and differently occurring timing edges.

BACKGROUND OF THE INVENTION

The present invention is directed to an integrated circuit (IC) chip for providing signals having different timing edges.

As is well known, it is often necessary to be able to create signals on an IC chip having different edge placements. Typically, such timing edges are provided by using delay elements to delay signals with respect to one another and by using logic functions to obtain different pulse widths. However, providing these delays and logic functions on an IC chip presents a number of problems. One problem which arises is a result of the difficulty of providing relatively large delays on an IC chip. The reason is that on-chip delays are severely affected by unpredictable processing variations as well as by voltage and temperature, which can cause the resulting delay provided to vary by as much as ±60%. Thus, when a large delay is required to be provided on an IC chip, this ±60% variation will be significant and may not be tolerable. A typical known solution is to provide this required long delay circuitry off-chip where accuracy can be more precisely controlled. However, this has the severe disadvantage of requiring more parts, more board space, and more expense.

An example of the problem associated with providing a relatively long on-chip delay on an IC chip is illustrated by the graphs in FIG. 1.

Graph A in FIG. 1 illustrates a typical clock C having a clock cycle time T with rising clock edges occurring at times T1 and T3, and falling clock edges occurring at times T2 and T4.

Graph B in FIG. 1 illustrates a FIRST DELAYED SIGNAL S1 produced by delaying clock C by an on-chip delay d1 which provides a relatively small delay (e.g., d1=0.10T). It is assumed in Graph B that d1 varies by ABOUT ±40% of d1, as indicated by Δd1.

Graph C in FIG. 1 illustrates a SECOND DELAYED SIGNAL S2 produced by delaying clock C by an on-chip delay d2 which provides a relatively large delay (e.g., d2=9T/10). Similar to d1 in Graph B, it is assumed in Graph C that d2 varies by about ±40% of d2, as indicated by Δd2.

As shown by Graph B in FIG. 1, the effect of Δd1 on the timing edges provided by S1 is relatively small and can easily be tolerated. This will be evident by noting that, for d1=0.10T, Δd1 will only amount to about 0.08T.

However, as shown by Graph C in FIG. 1, the effect of Δd2 on the timing edges of S2 is intolerable, since it can cause the rising edge of S2 to occur in the next clock cycle (after T3). This will be evident by noting that, for d2=0.09T, Δd2 will amount to about 0.72T. This will cause the rising clock edge of S2 to occur at about 1.26T (0.09T+0.36T), which is greater than the clock cycle time T. Note that this occurred assuming that Δd2 varies by only ±40% . Since this variation may typically be ±60% in the worst case, the provision of other than relatively small delays on a chip can present a serious timing problem. This is a primary reason why the prior art normally provides relatively long delays (such as those greater than T/2) off-chip where delay variations can be better controlled.

Another problem which arises in creating IC chip signals having different edge placements occurs because different logic functions are required to produce signals having different pulse widths. Since logic elements used to perform these different logic functions typically introduce different propagation delays, critical timing requirements may be compromised. For example, since a conventional OR gate may typically provide a different propagation delay from a conventional AND gate, different logical combinations of these OR and AND gates can produce significantly different path delays.

SUMMARY OF INVENTION

A broad object of the present invention is to provide improved methods and apparatus for creating IC chip signals having differing edge placements.

A more specific object of the present invention is to provide improved methods and apparatus for creating a relatively large on-chip delay on an IC chip.

A further object of the present invention is to provide the aforementioned methods and apparatus in an efficient and economical manner.

In a preferred embodiment of the present invention directed to accomplishing the above objects, a significant technical advance is obtained by advantageously creating "negative" on-chip delays which can be used as a substitute when large delays are required, whereby delay variations are maintained within tolerable limits, even for relatively large delays. In addition, in embodiments requiring the performance of logic operations, multiplexors are configured for use as a common logic element, whereby critical delays may be more accurately controlled.

The specific nature of the invention as well as other objects, advantages and uses thereof will become evident from the following description of a preferred embodiment of the invention in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a series of graphs illustrating problems that can occur using known on-chip delays for creating IC chip signals having different edge placements.

FIG. 2 is a block diagram illustrating how delays are conventionally provided on an IC chip.

FIG. 3 is a series of graphs illustrating the delays produced by FIG. 2.

FIG. 4 is a block diagram illustrating a preferred embodiment of the present invention for creating a relatively long delay on an IC chip.

FIG. 5 is a series of graphs illustrating the operation of FIG. 4.

FIG. 6 is a block diagram illustrating a preferred embodiment of the present invention for creating a clock signal having an early rising edge.

FIG. 7 is a series of graphs illustrating the operation of FIG. 6.

FIG. 8 is a block diagram illustrating a preferred embodiment of the present invention for creating an early pulse.

FIG. 9 is a series of graphs illustrating the operation of FIG. 8.

FIG. 10 is an alternate embodiment of FIG. 6.

FIG. 11 is an alternate embodiment of FIG. 8.

FIG. 12 is an embodiment incorporating the embodiments of FIGS. 10 and 11.

DESCRIPTION OF PREFERRED EMBODIMENTS

Like numerals and characters represent like elements throughout the figures of the drawings.

Referring to FIG. 2, shown therein is a block diagram illustrating how delays are typically provided on an IC chip, such as a VLSI chip. As indicated in FIG. 2, the chip includes a RAM (random access memory) 14, a flip-flop 16 and a latch 18. Of course, other circuitry is also provided on the chip, but is not shown since it is not pertinent to the present invention.

It will be assumed that RAM 14 in FIG. 2 requires the normal system clock C, that flip-flop 16 requires a clock C' having a rising edge which occurs a relatively short time d' after the rising edge of system clock C, and that latch 18 requires a clock C" having a rising edge which occurs a relatively long time d" after the rising edge of system clock C. The delay d' required for clock C' may typically be provided by an on-chip delay 20, and the delay d" required for clock C" may typically be provided by an on-chip delay 22. Graphs A, B and C in FIG. 3 respectively illustrate system clock C, flip-flop clock C' and latch clock C" provided by FIG. 2, and the delays d' and d" provided for C' and C", respectively.

Since the delay d' of delay 20 in FIG. 2 is relatively short, its worst case variations can be tolerated, as previously explained with respect to the first delayed clock C1 in FIG. 1. However, since delay d" of delay 22 is relatively long, its worst case variations could create the problem illustrated for the SECOND DELAYED CLOCK C2 in Graph C of FIG. 1, which illustrates how this worst case delay can cause the rising edge of the delayed clock to occur in the wrong clock cycle. One way of preventing this problem from occurring is to test delay 22 on each chip to make sure that its actual worst-case delay variation is within acceptable limits. This added testing is undesirable since it can significantly increase the manufacturing cost. Another way of solving this problem is to provide this relatively long delay 22 off-chip which is also undesirable, as pointed out previously.

FIG. 4 illustrates a preferred embodiment of the invention which provides a unique solution to the above described problem of providing an on-chip long delay by creating an on-chip "negative" delay on the chip which can be used instead of a required long delay when its worst case variations could cause a problem.

With reference to FIG. 4, illustrated therein is the same RAM 14, flip-flop 16 and latch 18 shown in FIG. 2. However, an important difference is the manner in which the long delay d" illustrated in Graph C of FIG. 3 is provided for latch 18.

As shown in FIG. 4, the system clock C is applied to a phase-locked-loop (PLL) 25, which may be of conventional form. PLL has inputs 25a and 25b and an output 25c. The system clock C is applied to input 25a and a feedback clock signal C_(f) is applied to input 25b. As is well known, a PLL exhibits the characteristic of automatically adjusting its phase so that signals applied to its inputs 25a and 25b are synchronized. Accordingly, PLL 25 will operate to synchronize the feedback clock signal C_(f) with the system clock C. This feedback clock signal C_(f) as well as system clock C may thus be used where a normal system clock C is required, such as for application to RAM 14.

Still with reference to FIG. 4, output 25c of PLL 25 is applied to a delay 28 whose output passes through clock buffer path 42 to become the clock C_(f) applied to RAM 14. As is conventional, this clock buffer path 42 includes inverters 30 which are used to permit the signal applied thereto to drive a plurality of other lines, such as generally indicated by lines 32. For simplicity of illustration, those lines 32 which are directed to other chip circuitry not pertinent to the present invention are shown terminated with dashes. As explained previously, PLL 25 causes C_(f) to be synchronized with the system clock C, thereby meeting the requirement that RAM 14 receive the system clock C.

So far, it has been described how a clock C_(f) synchronized with the system clock C is provided for RAM 14 by the synchronizing operation provided by PLL 25. It will next be described how clocks C' and C" are provided by FIG. 4 for flip flop 16 and latch 18, respectively.

As shown in FIG. 4, clock C' is provided for flip flop 16 by passing the output of delay 28 to flip flop 16 via delay 20 and a clock buffer path 44 including inverters 30. Clock buffer path 44 is chosen to provide the same delay as path 42. As a result, clock C' will be delayed from clock C_(f) (system clock C) by the delay provided by delay 20, since other delays (paths 42 and 44) are the same. The relatively small delay d' required by flip flop 16 is thus provided by choosing delay 20 equal to d'. Since d' is relatively small, it can be provided on-chip since its worst case variations will be tolerable, as explained previously.

Next to be described is the manner in which the preferred embodiment of FIG. 4 provides for on-chip implementation of the relatively long delay d" required between clock C" applied to latch 16 and clock C_(f) (system clock C) applied to RAM 14, despite worst case delay variations which would ordinarily make such an on-chip implementation intolerable.

As shown in FIG. 4, clock C" applied to latch 18 is obtained from PLL output 25c via clock buffer path 46. This clock buffer path 46, like path 44, is chosen to be equal to clock buffer path 42 located between the output of delay 28 and RAM 14. Clock C_(f) (the system clock C) will thus be delayed from C" by the amount of delay 28, since other delays (path 42 and 46) are the same. This permits the required relatively long delay d" for clock C" to be provided by choosing delay 28 equal to d_(n) =T-d", where T equals the clock period. For example, for a required relatively long delay d"=0.90T, delay 28 need merely provide the relatively small on-chip delay d_(n) =T-0.90T/10=0.10T, which would be tolerable even in view of worst case variations.

The operation of FIG. 4 is illustrated by the graphs of FIG. 5. Graph A in FIG. 5 illustrates the system clock C which is applied to input 25a of PLL 25. Graph A also illustrates feedback clock C_(f) which is applied to PLL input 25b, since PLL 25 synchronizes C_(f) with C. The requirement that the system clock C be applied to RAM 14 is thus met.

Graph B in FIG. 5 illustrates clock C' applied to flip-flop 16 which will be seen to be delayed by delay d' from the system clock C as a result of being applied thereto via delay 20 and clock buffer path 44. As mentioned previously, since the required delay d' is relatively small, its provision on-chip is tolerable.

Graph C in FIG. 5 illustrates clock signal C₂₅ appearing on PLL output 25c. Graph D in FIG. 5 illustrates the clock C₂₈ obtained after C₂₅ is delayed by delay 28. Note in Graphs C and D that, as is to be expected, C₂₈ is delayed from C₂₅ by d_(n), the delay provided by delay 28. With respect to the delay d_(p) shown between clock C₂₅ and the system clock C in Graphs A and B in FIG. 5, it will be understood that delay d_(p) represents the delay required to be provided by PLL 25 in order to produce synchronism between C and C_(f), as explained previously.

Graph E in FIG. 5 illustrates the resulting clock signal C" appearing at latch 16 in FIG. 4. It will be remembered that latch 16 requires the relatively long delay d" with respect to the system clock C (Graph C in FIG. 3). It will be understood from Graph E of FIG. 5 that this delay d" is obtained for clock C" as a result of the embodiment of FIG. 4 having provided the negative delay d_(n) for C" with respect to the system clock C, which is equivalent to having provided the relatively long delay d" using delay 22 in FIG. 2.

The previous description has illustrated how a clock having a long delay as well as a short delay relative to a system clock can advantageously be provided on an IC chip. It will next be explained with reference to FIGS. 6-9 how the present invention can also be advantageously employed for creating other types of IC chip signals.

In FIG. 6, similarly to FIG. 4, PLL inputs 25a and 25b receive the system clock C and a feedback clock C_(f), respectively. Also, similarly to FIG. 4, PLL output 25c is applied to a delay, which in FIG. 6 is designated as delay 68 providing a delay d_(k). As shown in FIG. 6, PLL output 25c is applied to an OR gate 70 along with the output of delay 68. As was the case for paths 42, 44 and 46 in FIG. 4, paths 72 and 74 are designed to provide the same delay. Since path 72 includes OR gate 70, an OR gate 71 is provided in path 74 to obtain better matching of the two paths, the unused input of OR gate 71 being connected to a log ic "0". As will be seen from the graphs of FIG. 7, FIG. 6 produces a clock C_(k) having a rising edge which occurs d_(k) earlier than the rising edge of the system clock C, and a falling edge which is coincident with the falling edge of C.

In FIG. 8 PLL 25 inputs 25a and 25b likewise receive the system clock C and a feedback clock C_(f), respectively, and PLL output 25 is likewise applied to a delay, which in FIG. 8 is designated as delay 78 providing a delay d_(p). As shown in FIG. 8, PLL output 25c is applied to one input of an AND gate 80, while the other input of AND gate 80 receives the output of delay 78. Also, like paths 72 and 74 in FIG. 6, paths 82 and 84 are designed to provide the same delay. Since path 82 includes an AND gate 80, an AND gate 81 is provided in path 84 in order to obtain better matching of the two paths, the unused input of AND gate 81 being connected to a logic "1". As will be seen from the graphs of FIG. 9, FIG. 8 produces a pulse P having a rising edge which occurs d_(p) earlier than the rising edge of system clock C, and a falling edge which is coincident with the rising edge of C.

FIGS. 10 and 11 illustrate alternate embodiments of FIG. 6 and 8, respectively, which employ appropriately configured multiplexors 90 in place of the OR gates 70 and 71 in FIG. 6, and AND gates 80 and 81 in FIG. 8.

Each multiplexor 90 in FIGS. 10 and 11 has a multiplexor selection input 90s, two other multiplexor inputs 90a and 90b, and a multiplexor output 90c. Each multiplexor 90 operates such that, when multiplexor selection input 90s is "1" (or true), the top multiplexor input 90a is selected at the multiplexor output 90c. On the other hand, when multiplexor selection input 90s is "0" (or false), the bottom multiplexor input 90b is selected as the multiplexor output 90c.

In FIG. 10 (which is an alternate embodiment of FIG. 6), it will be seen that a multiplexor 90 is substituted for OR gate 70 in path 72 of FIG. 6, and another multiplexor 90 is substituted for OR gate 71 in path 74. As shown in FIG. 10, the output of delay 68 is coupled to the selection input 90s of both multiplexors 90. Also, multiplexor input 90b in path 72 receives PLL output 25c, while multiplexor input 90a in path 72 receives a logic "1". In path 74, multiplexor inputs 90a and 90b receive a logic "1" and "0", respectfully. From the above described operation of multiplexor 90, it will be understood that the illustrated configurations of multiplexors 90 provided in paths 72 and 74 in FIG. 10 produces the same resulting output signals as shown in FIG. 7.

In FIG. 11 (which is an alternate embodiment of FIG. 7), it will be seen that a multiplexor 90 is substituted for AND gate 80 in path 82 of FIG. 8 and another multiplexor 90 is substituted for AND gate 81 in path 84. As shown in FIG. 11, the output of delay 78 is coupled to the selection input 90s of both multiplexors 90. Also, multiplexor input 90b in path 82 receives PLL output 25c, while multiplexor input 90a in path 72 receives a logic "0". In path 84, multiplexor inputs 90a and 90b receive a logic "1" and "0", respectfully. From the above described operation of multiplexor 90, it will be understood that the illustrated configurations of multiplexors 90 provided in paths 82 and 84 in FIG. 11 produces the same resulting output signals as shown in FIG. 9.

A significant advantage of the alternate embodiments of FIGS. 10 and 11 is that the use of multiplexors 90 therein (instead of OR and AND gates as in FIGS. 6 and 8) facilitates the combination of FIGS. 10 and 11 into the single embodiment shown in FIG. 12, wherein only a single PLL 25 is required. It will be understood that the use of multiplexors 90 in FIG. 12 prevents the occurrence of propagation differences which would restrict combination of the embodiments of FIGS. 6 and 8. For example, without the use of multiplexors 90 in FIG. 12, the desired matching of paths 72, 74 and 82, 84 would be difficult, if not impossible, to achieve. It will also be understood that variations in delays 68 and 78 will not create a significant problem, since they are relatively small and their variations will track one another as a result of their being on the same IC chip.

Although the present invention has been described with respect to particular preferred embodiment, it is to be understood that various modifications in construction and arrangement are possible within the scope of the invention. Accordingly, the present invention is to be considered as including all modifications and variations coming within the scope of the invention as defined by the appended claims. 

What is claimed is:
 1. In an integrated circuit chip having digital circuitry employing a system clock, improved on-chip circuitry for providing a predetermined signal having at least one differently occurring edge with respect to an edge of said system clock, said improved on-chip circuitry comprising:a phase-locked-loop having a first input, a second input and an output, said first input being coupled to said system clock; a delay element having one and coupled to said output of said phase-locked-loop, said delay element providing a delay substantially equal to the delay desired between said edge of said system clock and said differently occurring edge; a first path having one end coupled to the other end of said delay element, the other end of said first path being fed back to said second input of said phase-locked-loop, said phase-locked-loop being operative to synchronize the input signals applied thereto; a second path having a delay substantially equal to the delay of said first path, one end of said second path being coupled to said output of said phase-locked-loop, said predetermined signal being obtained from the other end of said second path; and logic circuitry in at least one of said paths for determining the occurrence of another edge of said predetermined signal.
 2. The integrated circuit chip of claim 1, wherein said first path includes an OR gate having a first input coupled to the output of said phase-locked-loop and a second input coupled to the output of said delay element.
 3. The integrated circuit chip of claim 2, wherein said second path includes an OR gate having a first input coupled to the output of said delay element and a second input coupled to a "0" logic level.
 4. The integrated circuit chip of claim 1, wherein said first path includes an AND gate having a first input coupled to the output of said phase-locked-loop and a second input coupled to the output of said delay element.
 5. The integrated circuit chip of claim 4, wherein said second path includes an AND gate having a first input coupled to the output of said delay element and a second input coupled to a "1" logic level.
 6. The integrated circuit chip of claim 1, wherein each of said first and second paths include a multiplexor having first and second multiplexor inputs and a multiplexor selection input for determining which of said first and second multiplexor inputs are selected for propagation through the multiplexor, wherein the multiplexor in said first path has a "1" logic level coupled to its first multiplexor input, a "0" logic level coupled to its second multiplexor input, and the output of said delay element coupled to its multiplexor selection input, and wherein the multiplexor in said second path has the output of said phase-locked-loop applied to its first multiplexor input, a "1" logic level coupled to its second multiplexor input, and the output of said delay element coupled to its multiplexor selection input.
 7. The integrated circuit chip of claim 6, wherein said multiplexors provide substantially the same propagation delay.
 8. The integrated circuit chip of claim 1, wherein each of said first and second paths include a multiplexor having first and second multiplexor inputs and a multiplexor selection input for determining which of said first and second multiplexor inputs are selected for propagation through the multiplexor, wherein the multiplexor in said first path has a "1" logic level coupled to its first multiplexor input, a "0" logic level coupled to its second multiplexor input, and the output of said delay element coupled to its multiplexor selection input, and wherein the multiplexor in said second path has the output of said phase-locked-loop applied to the first multiplexor input, a "0" logic level coupled to its second multiplexor input, and the output of said delay element coupled to its multiplexor selection input.
 9. The integrated circuit chip of claim 8, wherein said multiplexors provide substantially the same propagation delay.
 10. The integrated circuit chip of claim 7, including a third path including a multiplexor providing substantially the same propagation delay as the multiplexors in said first and second paths, wherein the multiplexor in said third path has the output of said phase-locked-loop coupled to its first multiplexor input, a "0" logic level coupled to its second multiplexor input, and the output of said delay element coupled to its multiplexor selection input. 